Bengaluru, India

Hi, I'm Soumitra.

Principal Engineer at Synopsys, building high-quality systems software in the Electronic Design Automation domain — with deep roots in C++, performance, and large-scale product development.

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  • 18+ years in software
  • C/C++ core expertise
  • EDA domain specialist
  • 2 US patents granted

01 About

I'm a Principal Engineer at Synopsys with a long track record in the EDA (Electronic Design Automation) industry, where correctness and performance are everything. I've worked across the full product life cycle — from marketing specification through to productized delivery — including cross-site product development.

I enjoy digging into hard, low-level problems: data models, netlist graphs, physical-hierarchy modelling, and the infrastructure that makes large designs tractable. I like exploring new ideas and I'm not limited by domain boundaries.

02 Skills

Languages

  • C++
  • C
  • Python
  • TCL
  • C-Shell

Hardware / HDL

  • Verilog
  • VHDL
  • SystemVerilog

Tools & Environment

  • Linux
  • GDB
  • Perforce
  • Git
  • ICC / ICC2

Domains

  • EDA
  • Physical Design
  • Compilers
  • Data Modelling

03 Experience

  1. Principal Engineer

    Synopsys Inc Feb 2024 — Present
    • Engineering and technical leadership in the EDA / physical-design space, continuing work across clock planning and large-scale C++ product development.

  2. Senior Staff Engineer

    Synopsys Inc Jan 2022 — Feb 2024
    • Senior individual-contributor role focused on complex physical-design features and cross-team product delivery.

  3. Staff Engineer

    Synopsys Inc Jan 2019 — Dec 2021
    • Clock-Trunk-Planning (CTP): early design-planning to create clock connections across physical hierarchies; stabilised functionality for customer deployment and built checkers to detect and report design clock issues.

  4. Senior Engineer

    Synopsys Inc Feb 2011 — Dec 2018
    • ICC2 Abstraction & Top-Level Optimization: interface-logic modelling, physical-object modelling, and merging abstract changes through the netlist graph; built distributed processing of independent blocks for better turnaround time.
    • ICC / ICC2 data model: lightweight model for physical data transformation with widespread usage; added double-patterning data-model support for advanced technology nodes.

  5. Senior Member Technical Staff

    Mentor Graphics Jan 2007 — Sep 2010
    • Backend compiler group supporting multiple frontend tools; produced structural netlists from Verilog, VHDL, and SystemVerilog.
    • Developed design-wide and synthesis rule checkers to reduce design cycle time.

  6. Summer Intern

    Mentor Graphics May 2006 — Jun 2006
    • Fragment parsing of files that may not follow standard Verilog syntax; earned a pre-placement offer.

04 Education & Certifications

B.Tech, Electrical, Electronics & Communications Engineering

Indian Institute of Technology, Kharagpur

2003 — 2007 · CGPA 8.16

Certifications

  • Python for Everybody — University of Michigan
  • Machine Learning — Stanford University
  • Managing Big Data with MySQL — Duke University
  • Building Web Applications in PHP — University of Michigan

05 Patents

Granted US patents in electronic design automation, assigned to Synopsys, Inc.

US 12,626,039 B2 Granted · In force

Associating physical design metrics of a circuit design with register transfer level representations of the circuit design

Filed 23 Sep 2022 · Granted 12 May 2026 · Application 17/951,840 · Assignee Synopsys, Inc.

Physical design metrics — timing, congestion, power and other layout-dependent measures — are computed for sub-circuits of an integrated circuit, then mapped back to the corresponding RTL source elements (lines, modules, and user-defined constructs). Aggregating these metrics per RTL element surfaces physical-design reality directly to front-end designers.

Co-inventors B. R. Rashingkar, A. Saunders, D. Chang, J. J. Loescher, O. W. Kozber, L. Tao, S. Majumder, C. Williams

US 12,073,156 B2 Granted · In force

Propagating physical design information through logical design hierarchy of an electronic circuit

Filed 15 Mar 2022 · Granted 27 Aug 2024 · Application 17/695,712 · Publication US 2022/0300687 A1 · Assignee Synopsys, Inc.

Physical design metrics from different parts of a circuit's physical design are propagated along the logic hierarchy of the design. By relating the physical design to the logic design, metrics are attributed to individual logic blocks and presented through a user interface that displays the logic hierarchy annotated with those metrics.

Co-inventors A. Jalota, A. Saunders, A. Kanagaraj, D. Chang, E. Rajendran, P. Gupta, R. Murgai, S. Majumder, V. Chatzi, B. R. Rashingkar

Google Patents → Justia →

06 Projects

A growing collection of small projects and experiments. More on the way.

07 Contact

Interested in my work or want to collaborate? Reach out.

Email majumder.soumitra@gmail.com LinkedIn /in/soumitra-majumder GitHub /maximgorkey-dev